Conventional manufacturing processes of semiconductor devices such as ICs and LSIs typically comprise forming a number of IC chips on a semiconductor silicon wafer and singulating it by dicing.
The demand for smaller electronic equipment with higher performance also leads to a demand for smaller IC chips with a higher degree of integration incorporated into the electronic equipment, but the density of integrated circuits in the direction of the plane of silicon substrates is close to the limit.
Wire bonding is a conventionally widely known technique for electrically connecting integrated circuits in IC chips to external terminals of the IC chips, and an alternative technique suitable for smaller IC chips has also recently been known, which comprises forming through-holes in a silicon substrate and connecting metal plugs as external terminals to integrated circuits via the through-holes (so-called, a method of forming a through-silicon electrode (TSV)). However, the technique comprising forming through-silicon vias alone cannot sufficiently meet the recent demand for IC chips with a higher degree of integration.
To overcome the drawbacks described above, a technique is known for improving the degree of integration per unit area of silicon substrates by providing multilayer integrated circuits in IC chips. However, the multilayer integrated circuits increase the thickness of the IC chips so that components of the IC chips must be thinned. Such components suggested to be thinned include, for example, silicon substrates, and this is a promising solution because it allows not only for reducing the size of IC chips but also for saving labor in the step of forming through-holes in silicon substrates during the preparation of through-silicon vias.
The semiconductor silicon wafer used in a method for manufacturing semiconductor device, are widely known to have a thickness of about 700 to 900 μm. Recently, for the purpose of miniaturization or the like of an IC chip, it has been attempted to reduce the thickness of the semiconductor silicon wafer to be 200 μm or less. To reduce the size of IC chips or for other purposes, attempts have recently been made to reduce the thickness of semiconductor silicon wafers to be 200 μm or less.
However, semiconductor silicon wafers having a thickness of 200 μm or less are so thin and therefore, components for manufacturing semiconductor devices using them as base materials are also so thin that such components are hard to stably support without damaging them during further processing or simply transferring or otherwise handling such components.
To solve the problems as described above, a known technique comprises temporarily bonding an unthinned semiconductor wafer having devices on its surface to a supporting substrate for processing using a silicone adhesive; thinning the semiconductor wafer by backgrinding; then drilling the semiconductor wafer to form through-silicon vias; and then debonding the supporting substrate for processing from the semiconductor wafer (see patent document 1). It is said that this technique allows for achieving resistance to grinding during backgrinding of the semiconductor wafer, heat resistance during an anisotropic dry etching process or the like, chemical resistance during plating or etching, smooth separation from the supporting substrate for processing at the final stage and low contamination on the wafer at the same time.
A technique for supporting a wafer by a carrier layer system is also known, comprising inserting a plasma polymer layer obtained by plasma deposition as a separation layer between the wafer and the carrier layer system in such a manner that the bond strength between the carrier layer system and the separation layer is greater than the bond strength between the wafer and the separation layer, whereby the wafer is readily debonded from the separation layer when the wafer is debonded from the carrier layer system (see patent document 2).
Another known technique comprises a temporary bonding step using a polyether sulfone and a tackifier, and a debonding step by heating (patent document 3).
Another known technique comprises a temporary bonding step using a mixture of a carboxylic acid and an amine, and a debonding step by heating (patent document 4).
Another known technique comprises bonding a device wafer and a carrier substrate under pressure via a heated bonding layer formed of a cellulose polymer or the like, and debonding the device wafer from the carrier substrate by heating and sliding apart them in a transverse direction (patent document 5).
Further, an adhesive film comprising syndiotactic 1,2-polybutadiene and a photoinitiator is known, wherein the bond strength of the film can be changed by irradiation (patent document 6).
Another known technique comprises temporarily bonding a carrier substrate and a semiconductor wafer using an adhesive formed of a polycarbonate, processing the semiconductor wafer, then irradiating it, and then debonding the processed semiconductor wafer from the carrier substrate by heating (patent document 7).
Further, a known technique for temporarily bonding a device surface of a device wafer having microdevices and a carrier substrate supporting the device wafer comprises temporarily bonding a peripheral region of the device surface and the carrier substrate with an adhesive via a fill layer not participating in bonding inserted between a central region of the device surface and the carrier substrate (patent document 8).